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ASIC Front End Verification Engineer - Hewlett Packard Enterprise HPE
Software Engineer
Lead ASIC front‑end verification using UVM and SystemVerilog, designing testbenches, driving simulation, and ensuring coverage to validate complex hardware designs.
About the role
Key Responsibilities
- Design, implement, and maintain UVM‑based testbenches for ASIC front‑end modules.
- Develop and execute simulation scenarios in SystemVerilog and Verilog to validate RTL behavior.
- Analyze waveform data, debug functional issues, and collaborate with RTL designers to resolve bugs.
- Generate and maintain coverage metrics, ensuring design coverage goals are met.
- Document verification plans, test cases, and results for traceability and audit purposes.
Requirements
- Strong experience with ASIC verification methodologies and UVM.
- Proficient in SystemVerilog and Verilog coding for testbench development.
- Hands‑on experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium).
- Excellent debugging skills and ability to interpret waveform data.
- Effective communication and teamwork in a cross‑functional engineering environment.