ASIC Core DFT Technical Lead - Scan, ATPG, Bist - cisco

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

As an ASIC Technical Lead, you will sit at the forefront of networking hardware innovation, directly shaping Cisco’s industry-defining Silicon One architecture. You will drive cutting-edge Design-for-Test (DFT) strategies, bridging the gap between front-end RTL, physical design, and post-silicon validation to ensure elite quality for some of the industry's most complex ASICs. In this role, your technical leadership and custom DFT solutions will directly fuel the next generation of best-of-breed routing and switching systems deployed across global enterprises, web-scale data centers, and service providers.

Key Responsibilities

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.

Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.

Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.

Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Qualifications

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience

Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.

Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime