Analog Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking an experienced Analog Design Engineer to develop cutting-edge die-to-die chiplet PHY IP solutions that power the future of AI computing. You'll work at the forefront of deep sub-micron technologies, collaborating with circuit architects and cross-functional teams to push the boundaries of analog/mixed-signal design. If you have a proven track record of delivering production-quality silicon and want to innovate at the heart of next-generation interconnects, join our team.

This role is remote, based out of any in North America .

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• A Analog/Mixed-Signal Design Engineer to develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks in deep sub-micron FinFET technologies.
• A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and silicon bring-up to production quality.
• A strong cross-functional partner who can work with architecture, analog, digital, verification, layout, and software teams to integrate and optimize AMS IP.

What we need

• 10+ years of analog/mixed-signal IC design experience in FinFET, including PLL/AMS design, with an MSEE/PhD or equivalent background.
• Strong track record in production tape-outs, silicon bring-up/testing, and hands-on use of industry-standard EDA tools with close layout collaboration.
• Deep experience in high-speed datacomm/SerDes and die-to-die PHY design, including Tx/Rx, DDR, PCIe, and USB PHY components.
• Collaborative, self-driven engineer with expertise across key circuits such as bias generators, amplifiers, LDOs, ADCs/DACs, oscillators, switched-cap circuits, plus familiarity with high-speed digital and equalization techniques like CTLE, DFE, and de-emphasis.

What you will learn

• How to push the limits of die-to-die chiplet PHY IP in advanced FinFET nodes, from architecture through high-volume production.
• How to co-optimize analog, digital, and layout to hit aggressive performance, power, and area tar