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Analog and RF Layout Engineer - Capgemini
Software Engineer
Senior Analog & RF Layout Engineer designing high‑performance RF ICs using Cadence Virtuoso, EM simulation, and S‑parameter extraction to meet stringent design rules and performance targets.
About the role
Key Responsibilities
- Design, review, and validate analog and RF IC layouts for high‑frequency applications, ensuring compliance with design rules and performance specifications.
- Perform EM simulation and S‑parameter extraction to predict and optimize RF performance, collaborating closely with circuit designers.
- Lead layout vs schematic reconciliation, resolve design discrepancies, and provide detailed documentation for manufacturing.
- Implement and maintain layout libraries, standard cell libraries, and design templates to streamline the design flow.
- Mentor junior layout engineers, conduct design reviews, and share best practices for RF layout techniques.
Requirements
- 5+ years of experience in analog and RF IC layout design, with a strong portfolio of high‑frequency projects.
- Deep understanding of RF design principles, impedance matching, and noise analysis.
- Excellent problem‑solving skills, attention to detail, and ability to work in a fast‑paced environment.
- Strong communication skills and experience mentoring junior engineers.