I am an aspiring ECE student, I love to work with digital electronics and to model them using Verilog, I wish to make my carrer in VLSI
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Assessing your cultural and operational fit
OpenPower-A2O-Core
December 3, 2025 – December 13, 2025
OpenPower-A2O-Core — GitHub repository
View ProjectSystem_Verilog_Practice
November 9, 2025 – November 14, 2025
System_Verilog_Practice — GitHub repository
View Project4-BIT_ALU_LATENCY_OPTIMIZED
November 6, 2025 – November 6, 2025
4-BIT_ALU_LATENCY_OPTIMIZED — GitHub repository
View ProjectIPCoreDesign
August 14, 2024 – August 17, 2024
IP (Intellectual Property) Core is used to provide pre-designed, reusable logic blocks that can be integrated into the design.
View ProjectRAM-Verilog
January 20, 2024 – January 22, 2024
This repo placed 2 different RAMs, async and sync: Async RAM: 1024 locations, 8-bit capacity. Enables independent read/write. Sync RAM: 1024 locations, precise clock-controlled access. Ideal for synchronized applications.
View ProjectCultural Fit Analysis
The candidate's project portfolio indicates a strong personal drive and interest in hardware design, which aligns with the technical demands of an FPGA Developer role. However, the lack of team-based projects or detailed descriptions makes it difficult to assess collaboration or broader cultural fit. The projects are primarily individual contributions.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. The candidate's project descriptions are brief, and no psychometric or English test results are available.