Hi! I am Sriram Vaibhav currently pursuing my B.Tech at IIIT Nagpur. I thrive on the exhilarating journey of learning and seeking fresh perspectives.
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FPGA Intern @Bitmapper Integration, Project Intern @NRSC, ISRO
Data Scientist
June 13, 2026 – Present
Reed-Solmon-Decoding
September 12, 2025 – September 12, 2025
Verilog implementation of the Reed Solmon decoding algorithm, comprising of the blocks , "SYNDROME", "CHEIN SEARCH", "BERLEYKEMP", and "FORNEY".
View ProjectViterbi-Decoder-213
September 10, 2025 – September 12, 2025
Verilog implementation of the Viterbi decoding algorithm. This decoder is designed for efficient error correction in digital communication systems. This includes Branch Metric Unit, Path Metric Unit, Add-Compare-Select Unit and Traceback Unit.
View ProjectPhase-Ambiguity-Resolver-using-Differential-Decoding
September 3, 2025 – September 12, 2025
Phase ambiguity in QPSK arises because the carrier can lock with 0°, 90°, 180°, or 270° rotation, causing bit errors. Differential decoding solves this by encoding data in the phase difference between consecutive symbols, so correct detection is possible regardless of absolute constellation rotation.
View ProjectZero-Crossing-Error-Timing-Detection
September 3, 2025 – September 12, 2025
Zero-crossing based symbol synchronization technique for timing error detection in digital communication systems.
View ProjectPAR_UniqueWord
August 26, 2025 – September 12, 2025
This project implements a digital communication system component designed to resolve phase ambiguity in Quadrature Phase Shift Keying (QPSK) signals. Phase ambiguity is a common issue in QPSK systems where a receiver's carrier recovery loop may lock onto one of four possible phase states, leading to incorrect symbol interpretation.
View ProjectDIP---BT22ECE056
January 19, 2025 – November 7, 2025
DIP---BT22ECE056 — GitHub repository
View ProjectCultural Fit Analysis
The candidate's projects are heavily focused on hardware description languages (Verilog) and digital communication systems, which is a significant mismatch for a 'Data Scientist' target role. While the candidate lists an 'FPGA Intern' and 'Project Intern @NRSC, ISRO' experience, the role is specified as 'Data Scientist', which contradicts the project portfolio. This indicates a lack of alignment with typical data science skill sets (e.g., Python, R, machine learning, statistics, data manipulation, visualization).
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. The candidate's project descriptions are technical but do not provide insight into collaboration, problem-solving approach, or communication style.