RTL Design & Verification Engineer with practical expertise in ASIC/FPGA design flows for end-to-end integration IPs
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Mini-Stereo-Digital-Audio-Processor
December 22, 2025 – Present
This repository is a documentation only placeholder for an academic project focused on the ASIC design flow, covering stages from RTL design through physical implementation and GDS generation using asap7 pdk
View ProjectDDR
September 21, 2025 – October 6, 2025
DDR memory controller implementation and verification
View ProjectSreekashUS.github.io
April 23, 2025 – April 23, 2025
SreekashUS.github.io — GitHub repository
View ProjectCDCL-Solver
September 23, 2023 – November 28, 2025
A small implementation of CDCL SAT solver that is used to solve 3SAT expressions
View ProjectCultural Fit Analysis
The candidate's projects are primarily personal and academic, focusing on hardware design, verification, and low-level software. This indicates a strong interest in the technical domain. However, the lack of team-based projects or detailed descriptions makes it difficult to assess collaboration or broader cultural fit. The projects align with a technical, problem-solving culture.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. The candidate's project descriptions are brief, and no psychometric or English test scores are available.