Sergiu Mosanu

FPGA Developer

https://www.opentalent.in/sergiu-mosanu

Ph.D. UVA HPLP

hplp

Key Strengths

Extensive personal project experience in FPGA development, including Verilog, SystemVerilog, VHDL, and Chisel.
Demonstrated interest in memory emulation, encryption, and CNN implementation on hardware.
Experience with hardware description languages (Verilog, SystemVerilog, VHDL, Chisel) and related tools (Tcl, Vivado HLS).

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio shows a strong focus on hardware description languages and FPGA-related development, which aligns well with the 'FPGA Developer' target role. The diversity of projects (memory emulation, encryption, CNN, network switches) indicates a broad technical curiosity and ability to tackle different challenges within the hardware domain. However, the candidate's experience level is listed as 0, and the only listed professional experience is a current role starting in the future (2026), which suggests a lack of professional experience. This significantly impacts cultural fit for a senior role requiring immediate impact.

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric or English test results are available.

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Assessing your cultural and operational fit

Projects

interviewing

May 24, 2023 – August 30, 2023

General coding exercises in preparation for technical interviews

View Project

ADXL-PI

October 25, 2022 – December 1, 2022

ADXL to Raspberry PI for Vibration acq

View Project

MEMulator

December 2, 2020 – April 17, 2023

Memory Emulation on FPGA Boards

View Project

PiMulator

June 5, 2019 – February 24, 2023

Processing in Memory Emulation

View Project

hopscotch

May 25, 2019 – April 8, 2025

Hopscotch: A benchmark suite for memory performance evaluation

View Project

axi_stream_tutorial

March 14, 2019 – April 10, 2019

VIVADO HLS Training AXI Stream interface

View Project

acomMNIST

October 12, 2018 – October 19, 2018

CNN MNIST

View Project

aes_chisel

November 7, 2017 – April 18, 2022

Implementation of the Advanced Encryption Standard in Chisel

View Project

Experimental_FPGA_computer

November 10, 2015 – November 20, 2018

This code implements a switch for interconnecting 50 FPGA boards in a topology based on the Hoffman–Singleton graph

View Project

trie-python-graphviz

April 25, 2015 – January 9, 2018

This is an Object Oriented implementation of a Trie in python. The class contains setter and getter methods, and implements several useful functionalities. In addition, the class can generate graphviz dot code, which can be used to visualize the Trie.

View Project

Key Strengths

Extensive personal project experience in FPGA development, including Verilog, SystemVerilog, VHDL, and Chisel.
Demonstrated interest in memory emulation, encryption, and CNN implementation on hardware.
Experience with hardware description languages (Verilog, SystemVerilog, VHDL, Chisel) and related tools (Tcl, Vivado HLS).

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric or English test results are available.

Sergiu Mosanu

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Experience

Projects

Key Strengths

Cultural & Operational Fit