CIT'2027 | Pre-Final year at Chennai Institute of Technology | B.E Electronics Engineering - VLSI Design and Technology
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Chennai Institute of Technology
Embedded Software Test Engineer
June 12, 2026 – Present
WaferWise-Edge-Wafer-Defect-Classification
March 6, 2026 – Present
"Edge-AI wafer defect classification using MobileNetV3-Small CNN. Achieves 92-93% accuracy with ~10ms inference, optimized for NXP eIQ deployment in Industry 4.0 environments."
View ProjectAI-POWERED-COLLISION-DETECTION-SYSTEM-USING-PYNQ-Z2-FPGA
October 27, 2025 – October 27, 2025
AI-POWERED-COLLISION-DETECTION-SYSTEM-USING-PYNQ-Z2-FPGA — GitHub repository
View ProjectVLSI-Design-Contest
October 24, 2025 – November 13, 2025
VLSI-Design-Contest — GitHub repository
View Project-RISC-V-SOC-Tapeout-Week-3
October 11, 2025 – October 11, 2025
Week 3 tasks for VSDBabySoC: Post-Synthesis Gate-Level Simulation (GLS) and Static Timing Analysis (STA) using Yosys, Icarus Verilog, GTKWave, and OpenSTA.
View ProjectRISC-V-SOC-Tapeout-Week-2
October 4, 2025 – October 4, 2025
Week 2 educational and practical modules for VSDBabySoC — an open-source RISC-V based System-on-Chip using SkyWater Sky130. Covers SoC fundamentals, functional modelling, and pre-synthesis simulation with Icarus Verilog and GTKWave.
View ProjectMicrowatt-OpenPOWER-HW-Design-Hackathon
September 23, 2025 – September 23, 2025
MicrowattSense: An open-source, low-power edge AI SoC built on the Microwatt POWER CPU. Integrates real-time sensor fusion, accelerators, and SKY130-ready RTL for reproducible, tapeout-ready designs. Perfect for education, research, and IoT innovation. 🚀💡
View ProjectRISC-V-SOC-Tapeout-Week-1
September 22, 2025 – September 27, 2025
Week 1 covers environment setup, open-source EDA tool installation, and Verilog RTL basics. Participants learn Linux commands, simulation flow, and simple testbenches, building a solid foundation for RTL design and upcoming synthesis tasks.
View ProjectSenbagaseelanV_RISC-V_SOC_TAPEOUT_VSD
September 19, 2025 – September 22, 2025
Documentation and implementation of the RISC-V SoC Tapeout Program by VSD, including design files, RTL, scripts, results, and supporting media related to Digital VLSI and SoC design flow.
View ProjectCultural Fit Analysis
The candidate's project portfolio is heavily focused on academic and personal VLSI/SoC design, which aligns well with the technical demands of an Embedded Software Test Engineer role. However, the lack of diverse project types or team-based experiences makes it difficult to fully assess cultural fit beyond technical alignment. The current experience level (0) and single listed role as 'Embedded Software Test Engineer' at Chennai Institute of Technology (with a future start date) suggest this is a very early-career candidate, which might require more mentorship and integration into a team culture.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. The candidate's project descriptions suggest a proactive and self-directed learning approach, but direct evidence of teamwork, communication, or problem-solving in a professional setting is limited.