SoC RTL Design Engineer @Arm | Building scalable SoCs from architecture to silicon
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ARM-software
Data Scientist
June 24, 2026 – Present
machine-learning-lab-EEEG513-bits
September 6, 2025 – September 25, 2025
Lab assignments for Machine Learning for Electronics Engineers (EEE G513) - Python implementations.
View Projectelectronic-voting-machine-verilog
July 14, 2025 – July 18, 2025
🚀 RTL design and testbench implementation of a Digital Electronic Voting Machine (EVM) using Verilog HDL. The EVM is modeled with a modular, FSM-based architecture suitable for FPGA or ASIC prototyping and educational use.
View Projectrtl-ahb-to-apb-bridge
July 14, 2025 – July 14, 2025
🚀 Synthesizable Verilog RTL implementation of an AMBA AHB-to-APB protocol bridge using a finite state machine (FSM).Designed for integration in SoC and IP subsystems that interface high-performance AHB masters with low-power APB peripherals.
View Projectrtl-fifo-designs
June 24, 2025 – July 15, 2025
🚀 RTL design of synchronous and dual-clock asynchronous FIFO buffers in Verilog, featuring flow control, pointer logic, and waveform-based validation.
View Projectrtl-protocol-designs
June 22, 2025 – June 24, 2025
⚙️ A curated RTL library of digital communication protocols — including AMBA(AHB/APB/AXI), UART, SPI, I2C, and FIFO-based buffering — designed in Verilog for synthesis, simulation, and SoC interconnect architecture.
View ProjectCultural Fit Analysis
The candidate's project portfolio is heavily focused on hardware description languages (Verilog, SystemVerilog) and digital design. While there is one machine learning project, the overall profile leans towards hardware engineering rather than data science. This indicates a potential mismatch with the 'Data Scientist' target role, suggesting a lower cultural fit for a pure data science position without further evidence of data-centric projects or experience.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. No psychometric or English test results are available.