Saw Xue Zheng

FPGA Developer

https://www.opentalent.in/saw-xue-zheng

Chronic Sleeper

Intel

Key Strengths

Extensive personal project experience in FPGA development, SystemVerilog, and VHDL.
Demonstrated practical application of hardware description languages through various projects (e.g., RISC-V core, VGA controller, image filters).
Current employment as an FPGA Developer at Intel indicates direct industry relevance and experience.
Familiarity with development tools and methodologies like FuseSoC and Verilator testbenches.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio shows a strong passion for digital design and FPGA development, aligning well with a specialized technical role. The diversity of personal projects (e.g., arcade game mimic, lowRISC primitives, RISC-V core) suggests a proactive and self-driven individual. However, the lack of team-based or collaborative project descriptions makes it difficult to assess cultural fit beyond individual technical drive. The candidate's experience is highly specialized, which is a good fit for a dedicated FPGA role but might limit adaptability to broader engineering contexts without further evidence.

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric or English test scores provided.

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Evaluating your skill match against the job requirements…

Assessing your cultural and operational fit

Projects

riscv-dev-container

September 19, 2021 – September 19, 2021

General development container for digital design and riscv cores

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lowrisc_prim

September 11, 2021 – September 11, 2021

lowRISC primitives separated out in its own repository for reuse in other projects

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riscv-core-dev

September 5, 2021 – September 20, 2021

RISCV core under development

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sv_novel_components

September 1, 2021 – September 1, 2021

Novel components from IEEE papers implemented as practice

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sv_common_components

August 14, 2021 – August 15, 2021

Common (and maybe generic) components for SystemVerilog with FuseSoc support

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rtl-starter

August 13, 2021 – August 13, 2021

FuseSoC template for starting a SystemVerilog design project with simple Verilator Testbench

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TheMathGroup

April 1, 2020 – April 1, 2020

TheMathGroup — GitHub repository

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CPAP_mask

February 11, 2017 – May 5, 2017

Arduino and PyQt5 codes for Capacitive CPAP Mask

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StopTheLightFPGA

September 14, 2016 – September 14, 2016

Mimics the cyclone arcade game where it spits out jackpot tickets if you stop the light when its right on top of you.

View Project

VHDL

September 8, 2016 – May 16, 2017

Everything related to VHDL design. Image Filters, PS/2 Keyboard Controller, VGA Controller...

View Project

Key Strengths

Extensive personal project experience in FPGA development, SystemVerilog, and VHDL.
Demonstrated practical application of hardware description languages through various projects (e.g., RISC-V core, VGA controller, image filters).
Current employment as an FPGA Developer at Intel indicates direct industry relevance and experience.
Familiarity with development tools and methodologies like FuseSoC and Verilator testbenches.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric or English test scores provided.

Saw Xue Zheng

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Experience

Projects

Key Strengths

Cultural & Operational Fit