Ritik Channa

FPGA Developer

https://www.opentalent.in/ritik-channa

IndiaMember since June 20, 2026

Key Strengths

Demonstrated interest in FPGA development through 'aes-verilog' and 'Verilog-Practice' projects.
Experience with Verilog HDL, which is directly relevant to the target role.
Exposure to C++ in embedded contexts ('smart_line_follower'), which can be beneficial for hardware-software co-design.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio shows a strong inclination towards personal projects, indicating self-motivation and a passion for learning. The diversity of projects, including Java, Python, and C++, alongside Verilog, suggests a broad technical curiosity. However, the lack of team-based projects or professional experience makes it difficult to fully assess cultural fit in a collaborative environment. The target role 'FPGA Developer' aligns well with the Verilog projects.

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.

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Projects

leotik

June 10, 2024 – June 12, 2024

leotik — GitHub repository

View Project

boilerplate-backend

June 2, 2021 – August 22, 2021

boilerplate-backend — GitHub repository

View Project

Server

October 10, 2020 – October 10, 2020

Server — GitHub repository

View Project

Assignment

October 4, 2020 – October 4, 2020

Assignment — GitHub repository

View Project

ffmpeg

May 14, 2020 – May 16, 2020

ffmpeg — GitHub repository

View Project

MyClassApi

April 4, 2020 – August 26, 2024

MyClassApi — GitHub repository

View Project

Verilog-Practice

August 11, 2018 – August 29, 2018

Verilog-Practice — GitHub repository

View Project

aes-verilog

February 3, 2018 – May 23, 2018

Implementation of AES in Verilog HDL

View Project

8085Emulator

January 18, 2018 – October 1, 2018

A fully functional 8085 Emulator with an easy gui.

View Project

smart_line_follower

March 5, 2017 – March 29, 2017

Smart car that follows line drawn path and switches to manual controls on detecting obstacle or explicitly by the operator

View Project

Key Strengths

Demonstrated interest in FPGA development through 'aes-verilog' and 'Verilog-Practice' projects.
Experience with Verilog HDL, which is directly relevant to the target role.
Exposure to C++ in embedded contexts ('smart_line_follower'), which can be beneficial for hardware-software co-design.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.

Ritik Channa

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Projects

Key Strengths

Cultural & Operational Fit