Rishab Sarayan

Embedded Software Test Engineer

https://www.opentalent.in/rishab-sarayan

Keep on Experimenting stuff

BengaluruMember since June 12, 2026

Key Strengths

Demonstrated interest in embedded systems and hardware description languages through personal projects (Systemverilog for Johnson's Counter, RISC-V Processor, 100daysofRTL).
Experience with SystemVerilog for both design (RISC-V Processor, 100daysofRTL) and verification (Johnson's Counter Layered TB), which is relevant for an Embedded Software Test Engineer role.
Basic programming exposure in C++ from a personal project.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's personal projects show a diverse interest, including web development (HTML, CSS, JavaScript), data analysis, and embedded systems. The focus on SystemVerilog projects aligns well with the 'Embedded Software Test Engineer' target role, indicating a potential cultural fit for a hardware-centric engineering environment. However, the lack of professional experience or team-based projects makes it difficult to fully assess cultural fit.

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback are available.

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Assessing your cultural and operational fit

Projects

Smera

February 1, 2026 – Present

Smera — GitHub repository

View Project

utk-birthday

July 7, 2025 – October 11, 2025

utk-birthday — GitHub repository

View Project

utk-birthday.github.io

June 30, 2025 – July 1, 2025

utk-birthday.github.io — GitHub repository

View Project

nextjs-geist-font-starter

June 29, 2025 – June 29, 2025

nextjs-geist-font-starter — GitHub repository

View Project

heart-disease

April 24, 2025 – April 24, 2025

heart-disease — GitHub repository

View Project

Video-Game-Analysis

March 28, 2025 – March 28, 2025

Video-Game-Analysis — GitHub repository

View Project

Johnsons-Counter-Layered-TB

December 28, 2024 – December 28, 2024

layered testbench for Johnsons Counter

View Project

RISC-V-Processor

December 13, 2024 – December 13, 2024

Single Stage RISC-V Processor

View Project

100daysofRTL

September 6, 2024 – September 6, 2024

RTL designs for practice

View Project

Bus-Reservation-C-Programming

August 5, 2023 – May 7, 2024

Bus-Reservation-C-Programming — GitHub repository

View Project

Key Strengths

Demonstrated interest in embedded systems and hardware description languages through personal projects (Systemverilog for Johnson's Counter, RISC-V Processor, 100daysofRTL).
Experience with SystemVerilog for both design (RISC-V Processor, 100daysofRTL) and verification (Johnson's Counter Layered TB), which is relevant for an Embedded Software Test Engineer role.
Basic programming exposure in C++ from a personal project.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback are available.

Rishab Sarayan

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Projects

Key Strengths

Cultural & Operational Fit