Richa Jha

Technical Leader (title received in 2025) in Intel’s Data Center & AI Group with 13+ years of experience in GPU/AI SoC performance modeling, SystemC TLM2.0, and C++. Currently leading pre-silicon GPU cache subsystem modeling and performance analysis. Deep expertise across DMA engines, matrix-multiplication engines, cache hierarchies, and SoC fabric, with a strong track record in designing micro-benchmarks, enabling HW/SW co-development, and correlating simulation insights with silicon behavior. Known for uncovering critical RTL issues early, improving simulation performance, and mentoring engineers to build robust modeling infrastructure for complex AI and GPU SoCs. ________________________________________ Publications (Internal Conferences) ________________________________________ • DTTC 2024: A Breakthrough Abstraction Technique for Speeding Up Pre-Silicon Software Performance Tuning • PnP Summit 2019 – SpringHill : Simulator to Silicon Story • DCG Innovation 2019 - A Novel Approach of crafting Micro-benchmarks for rapidly evolving AI HW in SoC • DTTC 2015 – A converged model for efficient Computer Vision IP HW/SW development • DTTC 2015 - Accelerating Computer Vision IP Validation using novel Simulator2RTL flow ________________________________________ Department Recognition Awards ________________________________________ • Early enabling of upcoming generation of GPU SoC Cache Verification, one of the highest hardware risk areas, by delivering golden reference model, uncovering critical hardware bugs and helping newly formed team ramp up quickly to help the compute die verification stay on track (2025) • Pre-Si Performance Simulator for Habana Gaudi2 - On-time pre-tape-out! (2021) • Pre-Silicon Software Readiness Award - AGENTS OF CHANGE - Achieved SW readiness before PO of SpringHill - Intel's first AI inference chip and completed workloads