I'm an electronic engineer graduated at University of Udine. Now I'm attending the 2nd level (Master degree) course of electronic engineering.
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Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
ParallelArchitectures
June 30, 2019 – June 30, 2019
Simple parallel architecture implementations
View Projectaes-communicator
September 28, 2018 – October 22, 2018
Cap protocol implementation in C for comunicate with FPGA for AES project
View Projectaes
September 28, 2018 – November 9, 2018
Implementation of AES encryption standard 128, 192 and 256 bits based on AES paper, "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard and "An ASIC Implementation of the AES SBoxes" article of Johannes Wolkerstorfer, Elisabeth Oswald, and Mario Lamberger
View ProjectaesCipher
September 26, 2018 – September 26, 2018
AES encryption standard 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard and "An ASIC Implementation of the AES SBoxes" of Johannes Wolkerstorfer, Elisabeth Oswald, and Mario Lamberger
View ProjectDataunit
September 20, 2018 – September 26, 2018
Data unit of AES 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard
View ProjectDatacell
September 20, 2018 – September 20, 2018
Datacell implementation of AES encryption standard 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard
View Projectkeygen
September 13, 2018 – September 23, 2018
Key generator of AES 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard
View Projectaes-sbox
September 12, 2018 – September 20, 2018
Dynamic SBOX in VHDL, based on "An ASIC Implementation of the AES SBoxes" article of Johannes Wolkerstorfer, Elisabeth Oswald, and Mario Lamberger
View ProjectCultural Fit Analysis
The candidate's projects are heavily focused on hardware description languages (VHDL) and low-level implementations, which aligns well with a specialized FPGA Developer role. The diversity of projects is limited to hardware design and related low-level programming, indicating a strong, focused interest in this domain. However, the lack of team projects or diverse technology exposure outside of VHDL/C++ might suggest a narrower scope of collaboration experience.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.