Rahul Kumar

FPGA Developer

https://www.opentalent.in/rahul-kumar-77

Member since June 24, 2026

Key Strengths

Extensive personal project experience in hardware description languages (Verilog, SystemVerilog) and related tooling (Scala, Python, Rust).
Demonstrated proficiency in developing SRAM generators and timing analysis tools, highly relevant for FPGA development.
Experience with UCIe implementation, indicating familiarity with modern chiplet interconnect standards.
Strong background in open-source contributions and tool development, showcasing initiative and practical application of skills.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's profile shows a strong inclination towards personal projects and open-source contributions, which can indicate self-motivation and a passion for technology. However, the lack of professional experience or team-based projects makes it difficult to fully assess cultural fit. The projects are highly specialized towards hardware design and tooling, aligning well with an FPGA Developer role.

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. The candidate's project descriptions are concise and technically focused, but no direct communication or collaboration examples are provided. No psychometric test results are available.

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Assessing your cultural and operational fit

Projects

klayout-lyp

September 23, 2025 – September 23, 2025

A parser for KLayout layer properties files (*.lyp)

View Project

rivet

May 30, 2025 – Present

A tool for flow management with a focus on simplicity and fine-grained checkpointing

View Project

uciephytest

May 8, 2024 – November 18, 2025

uciephytest — GitHub repository

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ucie

September 4, 2023 – Present

An open-source UCIe implementation

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inven

June 28, 2023 – September 11, 2023

grocery tracking

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stac-top

May 25, 2023 – July 31, 2025

The SRAM timing analysis chip for verifying SRAMs generated by SRAM22

View Project

sram22_sky130_macros

February 22, 2023 – Present

SKY130 SRAM macros generated by SRAM 22

View Project

psfparser

November 18, 2022 – January 30, 2025

A PSF reader written in Rust

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pyphotonics

February 24, 2022 – July 9, 2022

Tools for automated photonic circuit design.

View Project

sram22

January 9, 2022 – Present

A configurable SRAM generator

View Project

Key Strengths

Extensive personal project experience in hardware description languages (Verilog, SystemVerilog) and related tooling (Scala, Python, Rust).
Demonstrated proficiency in developing SRAM generators and timing analysis tools, highly relevant for FPGA development.
Experience with UCIe implementation, indicating familiarity with modern chiplet interconnect standards.
Strong background in open-source contributions and tool development, showcasing initiative and practical application of skills.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Rahul Kumar

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Projects

Key Strengths

Cultural & Operational Fit