Prasanna Sane
Data AnalystAI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
ASIC Engineer at Meta
Hi there! My name is Prasanna Sane and I graduated with Master’s degree in Electrical Engineering from Santa Clara University in June 2018. I'm working as ASIC Engineer, Design verification at Meta. I'm a Synopsys certified Design Verification Engineer with 8 years of DV experience and currently responsible for ASIC verification of multiple blocks and sub-systems of Meta's custom AI-accelerators and Network Interface Controller (NICs). I have previously worked at Western Digital (now SanDisk) where I was part of ASIC verification of 2 NVMe SSD controller generations with on-time tape-out, Axiado Corp- a hardware cybersecurity start up when I worked on block level verification of custom PCIe endpoint controller (gen3). I also have 2 years of professional experience as a Software Developer which has bolstered my Object-Oriented knowledge and I have completed Synopsys certifications for SystemVerilog, SV-Assertions and UVM 1.2 during my time at Santa Clara University. I am constantly looking for new challenges and opportunities across Design Verification positions. You can reach out to me by email/LinkedIn In-mail. Prasanna Sane prasssane@gmail.com
Santa Clara University
Master of Science (M.S.), Electrical and Electronics Engineering
January 1, 2016 – January 1, 2018
Gogte Institute of Technology
Bachelor of Engineering (BEng), Electrical, Electronics and Communications Engineering
January 1, 2010 – January 1, 2014
Meta
ASIC Engineer, Design Verification
December 1, 2023 – Present
Sunnyvale, California, United States · Hybrid
Western Digital
Staff Engineer-ASIC Design Verification
January 1, 2021 – December 1, 2023
Milpitas, California, United States
Axiado Corporation
ASIC Verification Engineer
November 1, 2018 – January 1, 2021
San Jose, California
SSR Labs
Design and Verification Intern
August 1, 2018 – October 1, 2018
San Francisco Bay Area
Santa Clara University School of Engineering Graduate Programs
TA-Grader
January 1, 2018 – March 1, 2018
Infosys
Senior System Engineer
June 1, 2016 – August 1, 2016
Infosys
System Engineer
June 1, 2014 – May 1, 2016
ASIC Verification of PCIe Transaction Layer with Config space
November 1, 2018 – Present
Designed and built scalable and reusable verification environment infrastructure to verify PCIe Transaction Layer. Its an ongoing project with DLL side ready. Highlights: - Can function as endpoint device or root complex - Can generate/catch InitFCs and UpdateFCs and respond smartly - Performs configuration enumeration, BARs read & allocation, power management, MSI setting & PCI express capabilities negotiation - Generated and catches unsupported requests & error messages. (In case of error injections) - More additions are under progress
ASIC Verification of enhanced, multiple PIT counters
October 1, 2018 – November 1, 2018
Designed and built scalable verification environment to verify custom PIT counters. Highlights: - System Verilog on Synopsys VCS - Modular reference model using classes - Typed mailboxes for message passing - Semaphores to control shared resources (same bus) - Functional and toggle coverage - Assertions
Verification Of 16x16 Router using SystemVerilog & UVM 1.2 (Synopsys VCS, DVE & Verdi)
May 1, 2018 – June 1, 2018
1. Successfully performed functional verification of given DUT (16x16 router) based on given spec sheet. Generated over 2,500 packets with manual seeds to reach ~100% coverage. Improved the effectiveness of test-bench by constrained random validations to reach corner cases. 2. Built a UVM 1.2 test environment to verify the same DUT with Master and Slave agents which contain their own sequencers, drivers and monitors. 3. Reached 100% functional coverage by driving over 2,000 constrained randomized transactions to DUT -Tools used: Synopsys VCS, Verdi3 and DVE
Deep learning with MATLAB
February 1, 2018 – March 1, 2018
I started this project by experimenting with MATLAB's AlexNet deep, convolution neural network and ended up with my own neural network. Following are the highlights: -Successfully trained AlexNet via transfer learning to recognize 14 different, custom object classes with 98% accuracy by using an image dataset consisting over 20,000 images, compiled by me. I started off with initial learning rate of 0.01, then gradually dropped it by 0.2. Training method used-stochastic gradient descent with momentum. -Built a simple neural network from scratch with 6 layers, trained using CIFAR-10 dataset with an accuracy of 70% -Since the deep learning is GPU intensive, I ran the training code on 2 different hardware systems (PC vs Laptop both equipped with NVIDIA GPU) and compared their training time. Turns out, NVIDIA GTX 1070 is 3.5x faster than NVIDIA GTX 960M
8-bit UART transmitter
January 1, 2018 – March 1, 2018
Implemented 8-bit UART transmitter on Xilinx Artix-7 FPGA using Verilog. Features: -8 bit data, 1 start bit, 1 stop bit, baud rate=9600, debug capabilities, eco-back on TeraTerm -Board used: Digilent Basys3 Issues Faced: -Since I used a board with switches and buttons to transmit data at a button press, Button Debouncing was major issue. For one press of the 'Send' button, I would get ~30 eco-backs. I used 2 different approaches to solve this issue. -First was to slow down the "spikes" using frequency divider. (Once you press the button, it generated several ON-OFF signals since its not ideal button) This worked partially. -Second approach was to count from button press till predetermined value and assign all ON-OFF signals as one ON signal. This worked effectively and I was able to get one letter eco-back
Schematics, Layouts and Static Timing Analysis
January 1, 2018 – March 1, 2018
->Built and Analyzed layouts of inverter, multi-input NAND gates, Domino logic and Manchester carry chain ->Performed schematic level static timing analysis of pipelined logic with flip-flops to verify Set-up and hold timing constraints. ->Improved delay of 5-input NAND gate by 2% using input remapping method. ->Built and tested 2x2 SRAM cell (schematic level) for read and write word operations ->Tool used: Synopsys Custom Compiler
High level synthesis
January 1, 2018 – February 1, 2018
Synthesized JPEG compressor and FIR filter from C++ and MATLAB with 2 different architectures to Verilog and implemented on Xilinx Artix-7 FPGA. ->Created my own test bench in C++ and MATLAB to verify the given design code. I learned intricacies of file manipulation in C++ during this task. ->Tool used: Xilinx Vivado HLS, Vivado 2016.2, MATLAB-R2017a and Microsoft Visual studio 2015
8x8 internet router
October 1, 2017 – December 1, 2017
->Designed 8x8 internet router using serialization and FIFO with my own arbiter to reduce gate area by 50% (25k gates vs given 50k) and meet given timing requirements (clock period=30ns) ->Successfully implemented on Xilinx FPGA (Artix-7 on Basys3 board) ->Modeling used- Verilog Behavioral modeling . ->Verified the design using system verilog. ->Tools used: Synopsys VCS and Synopsys Design compiler
Super resolution image reconstruction
December 1, 2013 – June 1, 2014
Implemented Bicubic single image super resolution algorithm using MATLAB which accepts satellite images as input and converts into higher resolution,magnified image. ->Key requirements: minimal memory consumption, relatively faster processing ->Tool used: MATLABr2014b
Line follower robot
November 1, 2012 – March 1, 2013
Its an autonomous,microcontroller based robot which follows black path from start point to destination.
UVM 1.2
Synopsys Inc
June 23, 2026 – Present
SystemVerilog Assertions
Synopsys Inc
June 23, 2026 – Present
SystemVerilog Testbench
Synopsys Inc
June 23, 2026 – Present
Cultural Fit Analysis
The candidate's professional experience is heavily concentrated in ASIC Design Verification and Electrical/Electronics Engineering, which is a significant mismatch for a 'Data Analyst' target role. While there is a 'Deep learning with MATLAB' project, it's an isolated instance and does not align with typical data analyst responsibilities or toolsets (e.g., Python, SQL, advanced statistics, data visualization, cloud platforms). The project diversity is strong within hardware engineering but lacks breadth in data analysis domains.
Soft Skills & Operational Fit
The candidate's experience as a TA-Grader and leading a team at Axiado Corporation suggests good communication and leadership potential. The detailed project descriptions indicate a methodical approach to problem-solving and a willingness to tackle complex issues (e.g., button debouncing).