Jhalak Patel
Backend EngineerAI Compilers @ NVIDIA
NVIDIA
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
AI Compilers @ NVIDIA
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
current: Tile IR (https://docs.nvidia.com/cuda/tile-ir/latest/index.html) Compiler developer. prev: TensorRT (https://docs.nvidia.com/tensorrt/index.html) developer.
Purdue University
Master’s Degree, Computer Engineering
January 1, 2014 – January 1, 2016
Indian Institute of Technology, Indore
Bachelor’s Degree, Electrical Engineering
January 1, 2009 – January 1, 2013
NVIDIA
Senior Deep Learning Compiler Engineer
April 1, 2025 – Present
NVIDIA
Senior Deep Learning Inference Engineer
September 1, 2019 – April 1, 2025
NVIDIA
Deep Learning Inference Engineer
November 1, 2017 – September 1, 2019
Intel Corporation
Software Engineer
May 1, 2016 – November 1, 2017
Folsom
Qualcomm
Software Engineer
July 1, 2013 – July 1, 2014
Bangalore, India
Indian Institute of Technology, Indore
Student Manager, Placement Office
June 1, 2011 – July 1, 2012
Indore, Madhya Pradesh, India
Distributed Hash Tables (DHTs) in Viceroy Network Topology
January 1, 2016 – May 1, 2016
• Implemented decentralized, distributed, constant degree peer-to-peer network for DHT-based application • Developed a simple test application for dynamic lookups, joining and leaving of server nodes • Used Akka APIs in Java/Scala to simulate highly scalable and dynamically distributed nodes network (approx.10000 nodes)
Variable Way (V-Way) Cache using Reuse Replacement Policy
August 1, 2015 – December 1, 2015
• Implemented V-Way cache using Ruby Memory Model in GEM5 Simulator • Implemented dynamic mapping between Tag-Store and Data-Store data structure to achieve global replacement (using Reuse Replacement) while maintaining constant L2 cache hit latency • Tested the implementation with SPEC CPU2006 benchmarks
XINU OS - Virtual Memory, Scheduling and Inter Process Communication (IPC)
August 1, 2015 – December 1, 2015
• Added Virtual Memory and Demand Paging Support to the XINU OS • Implemented time-shared and constant overhead scheduling using Multilevel Feedback queues • Implemented asynchronous IPC with callback function support in XINU (XINU stands for Xinu Is Not Unix, Developed at Xinu Lab, Purdue)
Parallel MapReduce using MPI and OpenMP
January 1, 2015 – May 1, 2015
• Implemented MapReduce to count number of words in multiple files using Open MP and MPI • Implemented Matrix multiplication and Binary Tree Traversal using the OpenMP and MPI • Performed Karp-Flatt and Iso-efficiency Analysis
Virtual Reality Application Using Oculus Rift and Leap Motion Controller
January 1, 2015 – May 1, 2015
• Created a VR App for Oculus Rift using Unity 3D where a person can view and move around furniture in an architectural environment • Integrated it with Leap Motion to detect the Hand Gestures for select and place, to move around the furniture • Implemented a cloud system where 3D furniture modules can be downloaded from cloud server when in play
SoC for the application of JPEG Decoder
October 1, 2014 – December 1, 2014
• Design and demonstrated a SoC that implements an application of JPEG Decoding • Implemented HW/SW partitioning using hardware accelerators/custom instructions, on-chip communication architecture to gain performance boost
Pipelined 8-Bit Wallace Tree Multiplier with Adaptive Clocking
August 1, 2014 – December 1, 2014
• Implemented 8 bit Wallace tree multiplier at scaled supply voltage with adaptive clock stretching • Created library of blocks such as Mirror Adder, True Single Phase Clock Flip-Flop, Doubled CMOS Clocked latch which operates at high speed, low power, and occupies an optimal area. • Used HSPICE and NanoSim for functional simulation as well as for Power, Area and timing analysis.
Cultural Fit Analysis
The candidate's background in high-performance computing, deep learning, and system-level programming aligns well with a demanding technical culture. The academic pedigree and experience at top-tier companies like NVIDIA, Intel, and Qualcomm suggest a drive for excellence and a fit for innovation-focused environments. The diverse personal projects, ranging from cache design to VR applications, indicate intellectual curiosity and a willingness to explore different technical domains, which can be a positive cultural asset. However, the projects are heavily academic/research-oriented, and the resume lacks explicit mention of collaboration or team-oriented achievements outside of the 'Student Manager' role, which is not technical.
Soft Skills & Operational Fit
The candidate's project descriptions indicate a strong problem-solving aptitude and a capacity for complex technical challenges. The progression through roles at NVIDIA suggests dedication and growth within a demanding technical environment. However, without specific psychometric or English test results, a direct assessment of communication, logical reasoning, work attitude, stress handling, and team collaboration is not possible. The project diversity suggests adaptability and a broad technical interest.