Jay Oza
FPGA DeveloperAhmedabad, Gujarat, IndiaMember since June 20, 2026
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
FastSim
November 7, 2020 – June 16, 2021
A tool to convert Verilog RTL file generated from Xilinx Vivado HLS to an equivalent C Code.
View ProjectImageSpec-An-Image-processing-benchmark-suite
May 4, 2020 – May 25, 2020
ImageSpec-An-Image-processing-benchmark-suite — GitHub repository
View Projectsystem_lab_assignment5
April 2, 2019 – April 2, 2019
system_lab_assignment5 — GitHub repository
View Projectlanguage_modelling
March 16, 2019 – March 31, 2019
language modelling using n-gram language model and neural probabilistic language model
View Projectsystem_lab_assignment4
March 14, 2019 – March 18, 2019
system_lab_assignment4 — GitHub repository
View Projectsystem_lab_assignment3
February 18, 2019 – March 1, 2019
system_lab_assignment3 — GitHub repository
View Projectpre_processing_nlp
February 5, 2019 – February 10, 2019
Text-processing, N-Gram, Collocation and Morphological analysis using NLTK
View Project2_player_game
January 22, 2019 – January 25, 2019
A 2 player game using fork, pipes and semaphores in C.
View ProjectVector_Quantization
September 25, 2018 – September 27, 2018
Vector Quantization using Linde Buzo and Gray
View ProjectEGVC
September 16, 2017 – September 16, 2017
Event website for registration and other purposes , created for college event EGVC(Eco-Green Vehicle Challenge 2016-17) which takes place at National level.
View ProjectCultural Fit Analysis
The candidate's projects show a strong inclination towards low-level programming, system-level tasks, and hardware-related development, which aligns with an FPGA Developer role. However, the project diversity is somewhat limited to C++ and Python, with only one explicit mention of Verilog. The 'EGVC' project indicates some web development exposure, but it's not directly relevant to the target role. The overall breadth of skills directly applicable to advanced FPGA development (e.g., VHDL, SystemVerilog, advanced synthesis, verification methodologies, specific FPGA architectures) is not extensively demonstrated.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. No psychometric or English test scores were provided.