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neural-net-chisel
January 17, 2022 – November 4, 2023
Implementation of a Neural Network in Chisel.
View ProjectPhysical-Design-Issues
November 24, 2021 – November 24, 2021
The process of converting the gate-level netlist to layout is termed as physical design. In physical design, there are various stages of design, various mandatory checks in each stage and involved various analysis and verifications. There are multiple challenges as we move to advanced nodes in physical design.
View ProjectUniversal-Shift-Register
November 21, 2021 – July 19, 2022
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
View ProjectSCOAP-Controllability-and-Observability
November 9, 2021 – November 12, 2021
This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs SCOAP Controllability and Observability of circuit..
View ProjectFault-collapsing-and-Fault-simulation
November 8, 2021 – November 16, 2021
This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsing, Parallel fault simulation, Deductive fault simulation.
View ProjectCultural Fit Analysis
The candidate's projects are heavily focused on VLSI design, digital logic, and hardware implementation. While these skills are technically strong, they do not directly align with a 'Data Scientist' target role. The project diversity is limited to this specific domain, suggesting a potential mismatch for the stated target role.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. No psychometric test results or interview feedback provided.