Bhavin Shah | OpenTalent | OpenTalent

Bhavin Shah

Bhavin Shah

Embedded Software Test Engineer

https://www.opentalent.in/bhavin-shah

Working as a DV Engineer - 2 at Qualcomm (earlier Alphawave Semi)

Qualcomm

AI is analyzing your overall score…

Identifying your key strengths…

Evaluating your skill match against the job requirements…

Assessing your cultural and operational fit

IndiaMember since June 13, 2026

https://www.opentalent.in/bhavin-shah

Top Skills

VerilogC++Systemverilog

Skills

VerilogC++Systemverilog

Experience

Qualcomm

Embedded Software Test Engineer

June 13, 2026 – Present

Projects

21-Days-of-RTL-Code

December 9, 2025 – December 9, 2025

Contains Basic Verilog Codes for initial RTL preparations

Router-1-3-Verilog-Design-

December 9, 2025 – December 9, 2025

Contains a 1*3 RTL Router Design , which takes a 63 byte packet, and arbitrates to a slave based on control information present in header field.

VLSI-Material-for-Interviews

December 9, 2025 – December 9, 2025

Contains various materials which are useful for cracking any VLSI interview

LISP-to-JavaScript-Expression-Compiler-Hand-Written-Lexer-Parser-AST-Visitor-

December 9, 2025 – December 9, 2025

A lightweight compiler frontend implemented in C++. It includes a tokenizer, recursive-descent parser, AST builder, AST transformer, and code generator. Converts LISP-style call expressions into JavaScript-style function calls. Demonstrates core compiler-design concepts such as lexing, parsing, AST transformation, and the visitor pattern.

SHA256-Generator-for-File-transfer-

December 9, 2025 – December 9, 2025

Contains SHA256 encrypted code generator in C

AHB2APB-Bridge-IP-Core-Design

December 9, 2025 – December 9, 2025

Contains a AHB to APB transaction bridge design, which takes AHB transactions as input, and converts it into a APB transaction depending upon Control information,

Axi_stream_processor

December 9, 2025 – December 9, 2025

Contains a Coding Assignment, which takes 3 Byte Axi stream input and give out a 8 byte Output.

Reconfigurable-AHB-Arbiter

December 5, 2025 – December 9, 2025

This project contains a Reconfigurable AHB Arbiter ,with multiple scheduling algorithms.

Key Strengths

Strong foundational knowledge in Verilog and SystemVerilog for RTL design.
Experience with various hardware design concepts including routers, arbiters, and bus protocols (AHB, APB, AXI Stream).
Demonstrated ability to implement compiler frontends, indicating strong C++ and algorithm skills.
Directly relevant experience as an 'Embedded Software Test Engineer' at Qualcomm, aligning with the target role.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's projects are heavily focused on hardware description languages (Verilog, SystemVerilog) and low-level programming (C++ for compiler design, SHA256). While this aligns with an embedded role, the diversity of projects outside of core hardware/low-level software is limited. The current role at Qualcomm as an Embedded Software Test Engineer is a strong fit for the target role, but the overall breadth of experience beyond this specific domain is not evident from the projects.

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. The candidate's project descriptions indicate a focus on technical implementation and problem-solving.