Masters student at NIT Rourkela, batch of 2026. 3 years experience at TCS under Cyber Security Practices vertical. Bachelors from Techno Main Salt Lake.
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National Institute of Technology
FPGA Developer
June 20, 2026 – Present
NITR_Hardware_Architecture_Lab
January 20, 2026 – Present
All codes for Hardware Architecture lab in Verilog and VHDL
View ProjectCustomerCare_Backend
January 11, 2026 – Present
Backend Java Project created using PostgreSQL and Spring Boot with Webflux.
View ProjectNITR-OnCampus-Flam_Backend
November 11, 2025 – November 12, 2025
Backend assignment project - QueueCTL for on campus placement for Flam
View ProjectNITR-APL
October 25, 2024 – November 5, 2024
All codes related to Advanced Programming Lab class in NIT Rourkela
View ProjectNITR-ASE
August 30, 2024 – December 15, 2024
All documents and codes related to Advanced Software Engineering class in NIT Rourkela
View ProjectNITR-DSAD
August 28, 2024 – November 2, 2024
All codes related to Data Structures and Algorithm Design class in NIT Rourkela
View ProjectDigitalToHandwriting
May 1, 2020 – May 2, 2020
This is just a pass-time project of me and a friend of mine, to convert our digital assignments to our own handwriting using code
View ProjectCristatus-Core
February 5, 2016 – May 3, 2016
This repository has the standard classes used in all other Cristatus projects.
View ProjectISC-English-Literature-Notes
January 19, 2016 – February 1, 2016
This repository contains notes to the chapters present in the English Literature Syllabus of ISC 2017.
View ProjectCultural Fit Analysis
The candidate's projects are primarily academic or personal, with a strong focus on university coursework. While there is a project involving Verilog and VHDL, the overall project portfolio is diverse but lacks depth in professional FPGA development. The listed 'FPGA Developer' role at National Institute of Technology is current but lacks details on responsibilities or achievements, making it difficult to assess alignment with a senior FPGA developer role. The candidate's experience level is listed as 0, which contradicts the 'FPGA Developer' role, suggesting a potential mismatch for a senior position.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. The candidate's project descriptions are brief, and there are no completed psychometric or English tests to provide insight into communication style or work attitude.