Upcoming semiconductor engineer! ROMantic at heart, but RAMdom in thoughts 🧡
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
StudentTrack-Development
May 15, 2026 – Present
This project's main objective is to manage all the student records and also track the changes.
View Project100-days-of-leetcode
February 11, 2026 – Present
100-days-of-leetcode — GitHub repository
View Project100-days-of-leetcode-problems
February 11, 2026 – Present
100-days-of-leetcode-problems — GitHub repository
View ProjectData-structures-and-algo
January 7, 2026 – Present
Journey of learning c prog from beginner to advanced
View ProjectOptimization-of-1-D-Convolution-IP-cores-using-Systolic-array-for-CNN-application
July 4, 2025 – July 9, 2025
Optimization-of-1-D-Convolution-IP-cores-using-Systolic-array-for-CNN-application — GitHub repository
View ProjectHDLbits-
June 30, 2025 – July 16, 2025
Practice problems and solutions from HDLBits — Verilog exercises for mastering digital design using Hardware Description Languages.
View Projectstudents_marks_application
October 13, 2021 – February 13, 2022
This is our CS Project. By Aravind, Arjun, and Ashwin.
View ProjectCultural Fit Analysis
The candidate's project portfolio shows a strong focus on hardware description languages (Verilog, SystemVerilog) and digital design, which aligns well with an FPGA Developer role. The inclusion of a few general programming projects (JavaScript, Python) indicates some breadth, but the primary interest appears to be in hardware. The candidate's experience level is 0, suggesting this is an entry-level or junior role target, which aligns with the personal project focus.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. No psychometric or English test scores are available, and project descriptions do not provide insight into collaboration or communication styles.