Aspiring VLSI Engineer | Digital & Analog Circuit Design | RTL Design | CMOS Design | JU ETCE’27
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Assessing your cultural and operational fit
Jadavpur University
VLSI Verification Engineer
June 12, 2026 – Present
axi4-lite-slave-verification
February 2, 2026 – Present
SystemVerilog AXI4-Lite Slave IP with Hazard-Stalled FSM. Verified with 2M+ cycle randomized regression and 'Snoop & Serialize' collision handling.
View Projectfifo_rtl
July 26, 2025 – Present
An robust Synchronous FIFO in Verilog RTL, featuring robust pointer-based logic for full/empty detection and support for simultaneous access.
View Projectuart_tx_rtl
July 22, 2025 – July 22, 2025
A parameterized and synthesizable UART Transmitter (TX) core in Verilog with a standard handshake interface.
View Projectuart_rx_rtl
July 20, 2025 – July 20, 2025
A robust, parameterizable UART Receiver (RX) designed in Verilog. Includes a flexible testbench for complete functional verification.
View ProjectCultural Fit Analysis
The candidate's projects are highly focused on VLSI design and verification, aligning well with the target role. However, the lack of diverse project types or team-based experience makes it difficult to fully assess cultural fit beyond technical alignment. The candidate's experience level is listed as 0, and the current role at Jadavpur University has a future start date, suggesting this is a very junior or entry-level candidate.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. The candidate's project descriptions are clear and concise, indicating good technical communication.