Anirudh

CMOS_Circuit_Design

February 16, 2026 – Present

This repository presents workflow for CMOS circuit design and SPICE simulation using the SkyWater SKY130nm technology node. It covers device-level modeling, analytical derivation of MOSFET current equations, and practical validation through SPICE simulations.

Engineering_simulations_Ansys

December 31, 2025 – Present

Collection of ANSYS simulations covering thermal modeling, airflow analysis, and semiconductor packaging with detailed workflows and results.

COD-Lab

August 5, 2024 – November 16, 2024

Instructions & Assignments for COD Lab - UE22EC352A

Single-Cycle-RISC-V-Processor

July 29, 2024 – August 1, 2024

This repository contains a single-cycle RISC-V processor designed in SystemVerilog for a 5th-semester project. It supports a subset of the RISC-V ISA and executes one instruction per clock cycle. The project includes SystemVerilog source files, testbenches, and documentation, providing a complete implementation ready for synthesis and simulation.

TSPC_Latch

May 31, 2024 – Present

Design and simulation of a True Single Phase Clock (TSPC) latch using Cadence Virtuoso. Focused on low-power VLSI design methodology with transistor-level implementation and performance analysis

6T_SRAM

February 13, 2024 – May 31, 2024

6T SRAM cell designed and simulated in Cadence Virtuoso using GPDK180nm CMOS technology. The project includes schematic design, and transient simulations to validate read/write operations

quantum_computing

December 30, 2023 – January 7, 2024

This repository contains my structured learning and implementation work in Quantum Computing, covering both theoretical foundations and practical circuit design using Python and IBM Qiskit

RISC-V-Assembly-level-programs

December 29, 2023 – September 5, 2024

This repository contains lab exercises completed during the 5th semester of engineering for the RISC-V course. These labs focus on practical applications of RISC-V architecture, utilizing the Ripes tool for simulation and assembly. Explore and enhance your understanding of RISC-V through hands-on exercises.

Layered-Testbench

December 9, 2023 – Present

This project implements a layered SystemVerilog testbench to verify a synchronous 4-bit adder. The verification environment is modular and self-checking, demonstrating core verification principles such as transaction-based stimulus, clock-aware driving, monitoring, and scoreboard-based result validation.

Vending_Machine_FSM

October 20, 2023 – November 4, 2023

The design and optimization of a vending machine FSM were accomplished using iVerilog, GTKwave, and Yosys